1. Field of the Invention
The invention relates to integrated circuit processing and, more particularly, to the introduction and patterning of interconnections on an integrated circuit.
2. Description of Related Art
Modern integrated circuits use conductive interconnections to connect the individual devices on a chip or to send and/or receive signals external to the chip. Popular types of interconnections include aluminum alloy interconnections (lines) and copper interconnections (lines) coupled to individual devices, including other interconnections (lines) by interconnections through vias.
A typical method of forming an interconnection, particularly a copper interconnection, is a damascene process. A typical damascene process involves forming a via and an overlying trench in a dielectric to an underlying circuit device, such as a transistor or an interconnection. The via and trench are then lined with a barrier layer of a refractory material, such as titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN). The barrier layer serves, in one aspect, to inhibit the diffusion of the interconnection material that will subsequently be introduced in the via and trench into the dielectric. Next, a suitable seed material is deposited on the wall or walls of the via and trench. Suitable seed materials for the deposition of copper interconnection material include copper (Cu), nickel (Ni), and cobalt (Co). Next, interconnection material, such as copper, is introduced by electroplating or physical deposition in a sufficient amount to fill the via and trench and complete the interconnect structure. Once introduced, the interconnection structure may be planarized and a dielectric material (including an interlayer dielectric material) introduced over the interconnection structure to suitably isolate the structure.
Copper has become a popular choice of interconnection material for various reasons, including its low resistivity compared with the resistivity of aluminum or aluminum alloys. Nevertheless, copper interconnection material is not without its own limitations. One limitation is that copper does not adhere well to dielectric material. The barrier material on the side walls of a via and trench as explained above provides adhesion to the adjacent dielectric material. However, in the damascene process described above, no barrier material is present on the top of the interconnect material and, consequently, copper is typically in direct contact with the dielectric material. Poor adhesion of copper material to dielectric material contributes to electromigration by the copper material during, for example, current flow.
A second problem encountered by copper interconnection material involves the difficulty in completely filling a via with copper material. In a typical electroplating introduction process, voids can appear in the via. The voids tend to aggregate and create reliability issues for the interconnection. The voids also increase the resistance of the via.
Another limitation of copper interconnection material as it is currently introduced is the tendency of the formed interconnection to blister or form hillocks due to subsequent annealing steps typically encountered in the formation of integrated circuit devices at the wafer level. These blisters or hillocks disrupt the otherwise planarized layers of interconnections over the wafer.
What is needed are improved interconnect structures and techniques for improving the introduction and properties of an interconnection structure.